ASIC/FPGA Development Engineer (Senior)

Job Locations UK-London
Posted Date 2 months ago(29/09/2023 19:08)
Job ID
# of Openings


V-Nova, a London based IP and software company, is dedicated to improving video quality and delivery by building a vast portfolio of innovative technologies based on the game-changing use of AI and parallel processing for data, video, imaging, and point cloud compression, with applications across several industries. This is achieved through deep-science R&D (500+ international patents) and the development of products that test, prove, and continuously enhance the technology portfolio.


V-Nova has contributed part of its IP to drive standardization of two video codec formats, MPEG-5 Part 2 (LCEVC (Low Complexity Enhancement Video Coding)), a low-complexity enhancement video and imaging codec, and SMPTE VC-6 (ST-2117), a high-performance AI-based video and imaging codec. V-Nova has developed multiple award-winning software products to kickstart the ecosystems for its technologies and allow their immediate deployment, addressing use cases in TV, media, entertainment, social networks, eCommerce, ad-tech, security, aerospace, defence, automotive and gaming.


We are committed to the extraordinary and rely on the talent of our high-performing diverse teams to provide innovative solutions and deliver what we promise. We have worked hard to create a company where talented, passionate people can thrive in a culture that values individual empowerment and excellence and achieves through teamwork. We are constantly on the lookout for exceptional individuals who thrive off solving challenging problems and want to make an impact. With ground-breaking technology, a fast-paced collaborative environment and major growth plans, there has never been a more exciting time to join us.


The company counts about 75 employees in its London Headquarters and 7 in Bangalore, India with a growing international presence.






V-Nova has developed an innovative approach to image and video compression that is driving major change in the encoding sector.

V-Nova seeks experienced individuals to join its compression development team for high speed development of 8K/4k and HD video processing on ASIC and prototyped on the FPGA platform. The ASIC/FPGA role reports directly to an Engineering Manager responsible for development, but the candidate must also interact with other development disciplines to create and integrate ASIC/FPGA technology into the product portfolio.


The company places high importance on a positive environment where talented individuals deliver exceptional products.  The candidate must share that vision and be passionate about “right first time” execution, as well as being a strong communicator and team player who strives to succeed. Furthermore, it is fundamental that the candidate solves problems in a consistent way so as not to compromise the strategic direction and is able to grasp an exciting new concept with genuine interest, trusting the innovators and driving execution through self-motivation.


  • Take the conceptual, high level mathematical work of V-Nova’s research group and architect RTL for ASIC implementation reuseable for FPGA prototyping.
  • Understand and maintain V-Nova's existing IP ASIC codec catalogue
  • Create test benches to verify RTL functionality using test vectors or random stimulus methodology
  • Create clear, concise and verifiable technical specifications
  • Synthesize design using synthesis and P&R tools, verifying against predetermined requirements.
  • Support the development of in-house python, octave or C++ models for RTL verification
  • Maintain and support current ASIC/FPGA deployments with customers and third parties


  • At least four years’ experience of ASIC and FPGA development in Verilog or VHDL including synthesis and static timing analysis for FMAX optimisation
  • Strong knowledge and experience of digital design principles and concepts for area and throughput optimization.
  • Strong understanding of AMD/Xilinx workflow (Vivado, HLS)
  • Good understanding of the Intel/Altera workflow (Quartus, Qsys and tcl)
  • Preferably experience of integrating 3rd party IP blocks (e.g. soft processors, SDI, PCie, DDR and network cores)
  • Preferably experience of design simulation in Riviera-Pro, Questa and scripting workflow
  • Willingness to independently and rapidly learn new subjects at the level of depth and rigor that is needed to progress development activities
  • An understanding of python, octave and C++ to support verification activities
  • Experience of development methodologies such as Agile and willingness to prioritise development activities in accordance with commercial priorities
  • A background in Broadcast video processing/encoding and signal processing would be advantageous but not essential
  • Proven ability to operate flexibly and effectively in a fast-paced, entrepreneurial start-up in which cross-functional teamwork and initiative are a must.
  • Keen attention to detail and quality focused


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