• FPGA Engineer

    Job Locations UK-London
    Posted Date 3 weeks ago(3 weeks ago)
    Job ID
    # of Openings
  • Overview

    V-Nova™ is a London-headquartered company providing advanced video and image processing hardware and software solutions. Its novel encoding technology, PERSEUS™, is based on principles underlying human vision. PERSEUS™ simultaneously offers significant improvements in compression, picture quality and processing speed with reduced power consumption. This is true in all practical commercial applications, such as on- and offline broadcasting, contribution, production and distribution at all quality levels, and within existing infrastructure. Founded in 2011 as part of a growing consortium of leading global partners, V-Nova™ serves multiple industry segments, including broadcasting, aerospace & defence, security, video conferencing, medical imaging and telematics.



    V-Nova has developed an innovative approach to image and video compression that is driving major change in the encoding sector.

    V-Nova seeks experienced individuals to join its compression development team for high speed development of 4k and HD video FPGA processing. The FPGA role reports directly to an Engineering Manager responsible for development, but the candidate must also interact with other development disciplines in to create and integrate FPGA technology into the product portfolio.


    The company places high importance on a positive environment where talented individuals deliver exceptional products.  The candidate must share that vision and be passionate about “right first time” execution, as well as being a strong communicator and team player who strives to succeed. Furthermore, it is fundamental that the candidate solves problems in a consistent way so as not to compromise the strategic direction and is able to grasp an exciting new concept with genuine interest, trusting the innovators and driving execution through self-motivation.



    • Take the conceptual, high level mathematical work of V-Nova’s research group and architect RTL for FPGA implementation
    • Create test benches to verify RTL functionality using test vectors or random stimulus methodology
    • Create clear, concise and verifiable technical specifications
    • Take personal responsibility for timescale estimation, task prioritisation and design accuracy
    • Support the development of in-house C++ models for RTL verification
    • Maintain and support current FPGA deployments with customers and third parties


    • At least five years’ experience of FPGA development in Verilog or VHDL including synthesis and static timing analysis for FMAX optimisation
    • Experience of integrating 3rd party IP blocks (e.g. soft processors, SDI, PCie, DDR and network cores)
    • Preferably experience of design simulation in Modelsim/Questa and scripting workflow
    • Strong understanding of Xilinx workflow (SDAccel, Vivado, HLS)
    • Strong understanding of the Altera workflow (Quartus, Qsys and tcl)
    • Experience in chip architecting, PLLs and floor planning
    • Preferably a background in Broadcast video processing/encoding and signal processing
    • Willingness to independently and rapidly learn new subjects at the level of depth and rigor that is needed to progress development activities
    • An understanding of C++ to support verification activities
    • Experience of development methodologies such as Agile and willingness to prioritise development activities in accordance with commercial priorities




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